System and method for dividing and synchronizing a processing task across multiple processing elements/processors in hardware

What is this patent about?

’596 is related to the field of load distribution and synchronization in multi-processor environments. Specifically, it addresses the overhead and latency issues associated with managing shared hardware resources, such as command queues, when multiple processing cores or disparate processors must coordinate their activities without overfilling buffers.

The underlying idea behind ’596 is to replace software-based synchronization primitives, like semaphores or mutexes, with a hardware-managed reservation register. By moving the tracking of available queue space into a dedicated hardware register that automatically decrements upon being read, the system eliminates the processing cycles typically wasted on software locks and shared memory variable updates.

The claims of ’596 focus on a system architecture where a reservation register acts as a gatekeeper for an input queue. When a processing element reads this register to check for space, the hardware performs an atomic decrement of the available count. The claims cover various configurations where secondary processors either notify a primary processor to issue a command or issue the command directly to the hardware queue on the primary's behalf once space is secured.

In practice, the invention functions by decoupling the act of reserving space from the act of submitting a command. When a processor reads the reservation register, it receives the amount of free space existing immediately prior to the read; if the value is sufficient, the hardware automatically subtracts the requested amount. This ensures that even if there is a delay between the reservation and the actual command submission, the space is guaranteed to be available, preventing queue overflow without requiring constant software polling.

This approach differs from prior solutions by shifting the burden of mutual exclusion from the operating system to the hardware logic. Unlike traditional methods that use a shared variable in memory, this system uses internal hardware arbitration to ensure that multiple simultaneous reservation attempts do not conflict. Furthermore, the hardware automatically restores the count when a command is consumed from the queue, providing a self-managing flow control mechanism that is transparent to the software layer.