Memory heaps in a memory model for a unified computing system

What is this patent about?

’809 is related to the field of heterogeneous computing architectures, specifically addressing the challenges of memory management in systems where a central processing unit and an accelerated processing device, such as a GPU, operate in a unified environment. Traditionally, these processors maintained separate address spaces, forcing programmers to manually move data between them, which created significant overhead and complexity. The invention seeks to streamline this by providing a more fluid, integrated approach to how these diverse processing units access and share physical memory resources.

The underlying idea behind ’809 is the implementation of a shared memory address space that utilizes specialized memory heaps to abstract the underlying physical hardware. Instead of requiring explicit data transfers, the system uses a mapper to direct memory operations to specific virtual pools—or heaps—based on a shared address. This allows pointers to be passed between the CPU and the accelerator without modification, effectively treating the disparate memory controllers and physical RAM modules as a single, cohesive resource with defined access properties.

The claims of ’809 focus on a method and system for mapping memory operations to one of a plurality of memory heaps based on a shared memory address (SMA). The independent claims highlight a mechanism where a mapper receives an address reference and determines the appropriate heap, which in turn dictates how the operation interacts with physical memory resources. Crucially, the claims specify that different memory attributes or access permissions can be applied to these heaps depending on which processor originated the request, allowing for fine-grained control over coherency and visibility.

In practice, the invention works by categorizing memory into functional types such as local, global, scratch, or coherent heaps. For instance, a coherent memory heap allows both the CPU and the accelerator to access the same data, with the system automatically handling the translation through an IOMMU or a system memory manager. Other heaps might be private to specific work-groups or replicated across threads to act as an extension of processor registers. This hierarchy ensures that high-performance graphics memory and high-capacity system memory can be utilized simultaneously and efficiently.

This approach differentiates itself from prior solutions by eliminating the need for the programmer to explicitly marshal data between separate device memories. By using a unified memory model where the mapping result is provided directly to the requesting processor, the system hides the complexity of physical memory location and hardware-specific protocols. Unlike conventional systems that treat the GPU as a peripheral with a disconnected memory space, this invention enables the accelerator to participate in the system's paging and protection schemes as a first-class citizen.