Stage circuit and organic light emitting display using the same

What is this patent about?

’593 is related to the field of flat panel display drivers, specifically stage circuits used within a scan driver for organic light emitting displays (OLED). In high-resolution displays, the complexity and transistor count of scan drivers directly impact manufacturing yield and the stability of the scan signals. Traditional designs often require numerous transistors and multiple initialization signals, which can limit the available time for supplying scan signals and increase the overall footprint of the display circuitry.

The underlying idea behind ’593 is to minimize the transistor count and eliminate the need for dedicated initialization signals by using a dual-node control architecture that relies solely on two non-overlapping clock signals. By cross-coupling the drivers for these two nodes, the circuit can use the clock signals themselves to both trigger the output and reset the internal state. This approach ensures that the output terminal is either tied to a stable power supply or the active clock signal, preventing the output from floating without requiring complex auxiliary reset logic.

The claims of ’593 focus on a stage circuit configuration where an outputting unit is governed by a first node and a second node to selectively pass either a first power supply voltage or a third input terminal signal to the output. A critical feature of the independent claims is the direct clock control mechanism, where the signal from the third input terminal (typically a clock) directly drives the gate of a transistor within the first driver to regulate the voltage at the second node. This specific interaction allows the driver to synchronize the charging and discharging of the control nodes without external timing pulses.

In practice, the first driver uses a transistor gated by the second input terminal to sample the start signal or a previous stage's output onto the second node. Simultaneously, the second driver utilizes the voltage at this second node to pull the first node to a low state, which activates a pull-up transistor to stabilize the output. When the clock signal at the third input terminal transitions, it is passed through to the output terminal to serve as the scan signal, while also triggering the internal transistors to reset the nodes for the next cycle.

This implementation differs from prior approaches by significantly reducing the component count, utilizing as few as seven transistors to achieve full scan functionality. By employing a self-resetting mechanism where the second driver monitors the second node to control the first node's state, the invention avoids the overhead of global reset lines. Furthermore, the design supports bidirectional scanning through a simple input selection stage, allowing the display to shift data in either direction while maintaining the same streamlined internal logic.