The detailed information for PTAB case with proceeding number IPR2018-00756 filed by Intel Corporation against Godo Kaisha IP Bridge 1 on Mar 7, 2018. This includes filing dates, application numbers, tech centers, patent numbers, and current case status.

Case Details

Proceeding Number
IPR2018-00756
Filing Date
Mar 7, 2018
Petitioner
Intel Corporation
Respondent
Godo Kaisha IP Bridge 1
Status
Institution Denied
Respondent Application Number
09469498
Respondent Tech Center
2800
Respondent Patent Number
6346736
Institution Decision Date
Oct 9, 2018

Proceeding Documents

The table below shows documents filed in the case, listing each document name, filing date, document type, and filing party. Tracking these filings indicates the activity of the parties involved in the case, and the types of documents filed can provide insights into the legal strategies being employed.


Document NameFiling DateCategoryFiling Party

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Trial Instituted Document

Oct 9, 2018PAPERBOARD

Decision Granting Patent Owner's Unopposed Motion to Withdraw Counsel and Change Designation of Lead and Back-Up Counsel

Jul 19, 2018PAPERBOARD

U.S. Patent No. 5,731,623 - Ishimaru

Jul 11, 2018EXHIBITPATENT OWNER

Patent Owners Preliminary Response

Jul 11, 2018PAPERPATENT OWNER

File History of U.S. Patent No. 6,130,139

Jul 11, 2018EXHIBITPATENT OWNER

U.S. Patent No. 5,663,588 - Suzuki

Jul 11, 2018EXHIBITPATENT OWNER

Transcript of Deposition of John Bravman

Jul 11, 2018EXHIBITPATENT OWNER

Declaration of Joseph B. Palmieri

Jul 11, 2018EXHIBITPATENT OWNER

Patent Owner's Updated Mandatory Notice

Jun 7, 2018PAPERPATENT OWNER

Patent Owner's Unopposed Motion to Withdraw Counsel and Change Designation of Lead and Back-Up Counsel

Jun 7, 2018PAPERPATENT OWNER

Patent Owner's New Power of Attorney

Jun 7, 2018PAPERPATENT OWNER

Notice of Accord Filing Date

Apr 11, 2018PAPERBOARD

Patent Owner's Power of Attorney

Mar 28, 2018PAPERPATENT OWNER

Patent Owner's Mandatory Notices

Mar 28, 2018PAPERPATENT OWNER

PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,346,736

Mar 7, 2018PAPERPETITIONER

Effect of scaling of interconnections on the time delay of VLSI circuits (Saraswat)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 5,107,320 (Iranmanesh)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 4,519,128 (Chesebro)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 5,733,812 (Ueda)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 5,814,848 (Oshima)

Mar 7, 2018EXHIBITPETITIONER

Some Problems of MOS Technology (Appels)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 4,960,725 (Noguchi)

Mar 7, 2018EXHIBITPETITIONER

Petitioner's Power of Attorney

Mar 7, 2018PAPERPETITIONER

Declaration of Dr. John C. Bravman

Mar 7, 2018EXHIBITPETITIONER

Curriculum Vitae of Dr. John C. Bravman

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 6,346,736

Mar 7, 2018EXHIBITPETITIONER

File History of U.S. Patent No. 6,346,736

Mar 7, 2018EXHIBITPETITIONER

Assignment History U.S. Patent No. 6,346,736

Mar 7, 2018EXHIBITPETITIONER

Sedra, Adel S., Microelectronics Circuits

Mar 7, 2018EXHIBITPETITIONER

Dorf and Tallarida, Pocket Book of Electrical Engineering Formulas

Mar 7, 2018EXHIBITPETITIONER

Uyemura, Fundamentals of MOS Digital Integrated Circuits

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 4,571,819 (Rogers)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 5,702,976 (Schuegraf)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 4,957,590 (Douglas)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 5,976,939 (Thompson)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 6,165,826 (Chau)

Mar 7, 2018EXHIBITPETITIONER

Cramming More Components Onto Integrated Circuits (Moore)

Mar 7, 2018EXHIBITPETITIONER

U.S. Patent No. 4,786,609 (Chen)

Mar 7, 2018EXHIBITPETITIONER

Matsushita Electric Becomes Panasonic Corporation

Mar 7, 2018EXHIBITPETITIONER