The detailed information for PTAB case with proceeding number IPR2019-00834 filed by Intel Corporation against Institute of Microelectronics, Chinese Academy of Sciences on Mar 19, 2019. This includes filing dates, application numbers, tech centers, patent numbers, and current case status.

Case Details

Proceeding Number
IPR2019-00834
Filing Date
Mar 19, 2019
Petitioner
Intel Corporation
Respondent
Institute of Microelectronics, Chinese Academy of Sciences
Status
Institution Denied
Respondent Application Number
13577942
Respondent Tech Center
2800
Respondent Patent Number
9070719
Institution Decision Date
Oct 4, 2019

Proceeding Documents

The table below shows documents filed in the case, listing each document name, filing date, document type, and filing party. Tracking these filings indicates the activity of the parties involved in the case, and the types of documents filed can provide insights into the legal strategies being employed.


Document NameFiling DateCategoryFiling Party

Alert me when new update on this case

DECISION Denying Petitioner¿¿¿s Request on Rehearing of Decision Denying Institution of Inter Partes Review 37 C.F.R. ¿¿ 42.71(d)

Jun 19, 2020PAPERBOARD

Petitioners Updated Mandatory Notice

Apr 8, 2020PAPERPETITIONER

Petitioner's Request for Rehearing

Nov 4, 2019PAPERPETITIONER

Decision Denying Institution

Oct 4, 2019PAPERBOARD

Declaration of Etai Lahav in Support of Patent Owner's Motion for Pro Hac Vice Admission

Aug 2, 2019EXHIBITPATENT OWNER

Patent Owner's Updated Exhibit List

Aug 2, 2019PAPERPATENT OWNER

Patent Owner's Motion for Pro Hac Vice Admission Under 37 C.F.R. ¿¿ 42.10(c) - Etai Lahav

Aug 2, 2019PAPERPATENT OWNER

Affidavit in Support of Petitioner's Motion for Pro Hac Vice Admission of C. Campbell

Aug 1, 2019EXHIBITPETITIONER

Petitioner's Motion for Pro Hac Vice Admission of C. Campbell and Updated Exhibit List

Aug 1, 2019PAPERPETITIONER

Ex. 1041 - Certified English Translation of Pat. Pub. No. PCT2008114341

Aug 1, 2019EXHIBITPETITIONER

Patent Owner's Preliminary Response

Jul 10, 2019PAPERPATENT OWNER

Patent Owner's Exhibit List

Jul 10, 2019PAPERPATENT OWNER

Bill Dally, Life After Moore¿¿¿s Law, Apr. 29, 2010, available at https://www.forbes.com/2010/04/29/moores-law-computing-processing-opinions-contributors-bill-dally.html#7ce473c82a86

Jul 10, 2019EXHIBITPATENT OWNER

Prof. Tsu-Jae King Liu, Planar Bulk CMOS Scaling to the End of the Road (Nov. 2012)

Jul 10, 2019EXHIBITPATENT OWNER

P. Packan, et. al., High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors, IEEE ELECTRON DEVICES MEETING (2009)

Jul 10, 2019EXHIBITPATENT OWNER

Digh Hisamoto, et. al., A Folded-channel MOSFET for Deep-sub-tenth Micron Era, IEEE ELECTRON DEVICES MEETING (1998)

Jul 10, 2019EXHIBITPATENT OWNER

H. Kawasaki, et. al., Challenges and Solution of FinFET Integration in an SRAM Cell and Logic Circuit for 22nm node and beyond, IEEE ELECTRON DEVICES MEETING (2009)

Jul 10, 2019EXHIBITPATENT OWNER

T. Ghani, et. al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS transistors, IEEE ELECTRON DEVICES MEETING (2003)

Jul 10, 2019EXHIBITPATENT OWNER

S. Tyagi, et. al., An Advanced Low Power, High Performance, Strained Channel 65nm Technology, IEEE ELECTRON DEVICES MEETING (2005)

Jul 10, 2019EXHIBITPATENT OWNER

Edward J. Nowak, et al., Turning Silicon On Its Edge [double gate CMOS/FinFET technology], 20 IEEE CIRCUITS & DEVICES MAG. 20-31 (2004)

Jul 10, 2019EXHIBITPATENT OWNER

Xuejue Huang, et. al., Sub-50 nm P-channel FinFET, 48 IEEE TRANSACTIONS ON ELECTRON DEVICES, 880-886 (May 2001)

Jul 10, 2019EXHIBITPATENT OWNER

U.S. Patent No. 7,402,856

Jul 10, 2019EXHIBITPATENT OWNER

Nick Lindert, et. al., Sub-60-nm quasi-planar FinFETs fabricated using a simplified process, 22 IEEE ELECTRON DEVICE LETTERS, 487-489 (Oct. 2001)

Jul 10, 2019EXHIBITPATENT OWNER

Yang-kyu Choi, et. al., FinFET process refinements for improved mobility and gate work function engineering, IEEE ELECTRON DEVICES MEETING, 259-262 (Dec. 2002)

Jul 10, 2019EXHIBITPATENT OWNER

Daewon Ha, et. al., Molybdenum Gate Hfo/Sub 2/ CMOS Finfet Technology, IEEE ELECTRON DEVICES MEETING (2004)

Jul 10, 2019EXHIBITPATENT OWNER

Huaxiang Yin & Qiuxia Xu, Design Considerations of the Sub-50nm Self-Aligned Double Gate MOSFET with a New Channel Doping Profile, 2001 6TH INT¿¿¿L CONF. ON SOLID-STATE AND INTEGRATED CIRCUIT TECH. PROC. (Cat. No.01EX443), Shanghai, China, 535-538 (2001)

Jul 10, 2019EXHIBITPATENT OWNER

Email correspondence from McFarland to the Patent Trial and Appeal Board, dated February 20, 2019.

Jul 10, 2019EXHIBITPATENT OWNER

Email correspondence from the Patent Trial and Appeal Board to McFarland, dated March 25, 2019.

Jul 10, 2019EXHIBITPATENT OWNER

Denial of Intel Corp. (China)¿¿¿s Invalidation Request Against CN201110240931.5, dated February 3, 2019.

Jul 10, 2019EXHIBITPATENT OWNER

Certified English Translation of Int¿¿¿l Pub. No. WO 2008/114341 (¿¿¿Okuno PCT¿¿¿)

Jul 10, 2019EXHIBITPATENT OWNER

C. H. Lee, et. al., Novel Body Tied Finfet Cell Array Transistor DRAM With Negative Word Line Operation For Sub 60nm Technology And Beyond, IEEE SYMP. ON VLSI TECH. DIG. OF TECHNICAL PAPERS (2004)

Jul 10, 2019EXHIBITPATENT OWNER

Bin Yu, et. al., FinFET scaling to 10 nm gate length, IEEE ELECTRON DEVICES MEETING (2002)

Jul 10, 2019EXHIBITPATENT OWNER

Huaxiang Yin & Qiuxia Xu, CMOS FinFET Fabricated on Bulk Silicon Substrate, 24 CHINESE J. OF SEMICONDUCTORS 4 (Apr. 2003)

Jul 10, 2019EXHIBITPATENT OWNER

FINFET EXTENDING MOORE¿¿¿S LAW (LexInnova, 2015)

Jul 10, 2019EXHIBITPATENT OWNER

Excerpt from MERRIAM-WEBSTER¿¿¿S COLLEGIATE DICTIONARY (11th ed. 2006)

Jul 10, 2019EXHIBITPATENT OWNER

U.S. Patent No. 6,797,593

Jul 10, 2019EXHIBITPATENT OWNER

U.S. Patent Application Pub. No. 2012/0329220

Jul 10, 2019EXHIBITPATENT OWNER

U.S. Patent No. 5,651,857

Jul 10, 2019EXHIBITPATENT OWNER

Intel Corporation v. Institute of Microelectronics, Chinese Academy of Sciences, IPR2018-01574, Paper No. 18 (P.T.A.B. Mar. 29, 2019)

Jul 10, 2019EXHIBITPATENT OWNER

Intel Corp. (China)¿¿¿s Invalidation Request Against CN201110240931.5, dated March 26, 2018.

Jul 10, 2019EXHIBITPATENT OWNER

Notice of Transmission of Intel Corp. (China)¿¿¿s Memorandum in Support of the Invalidation Request Against CN201110240931.5, dated May 8, 2018.

Jul 10, 2019EXHIBITPATENT OWNER

Machine Translation of JP 2008/114341 provided by Japan Platform for Patent Information

Jul 10, 2019EXHIBITPATENT OWNER

Notice of Accord Filing Date

Apr 10, 2019PAPERBOARD

Patent Owner's Power of Attorney

Apr 9, 2019PAPERPATENT OWNER

Patent Owner's Mandatory Notice

Apr 9, 2019PAPERPATENT OWNER

U.S. Patent Application Pub. No. 2009/0309141 ("Okuno")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2008/0251934 ("Mandelman")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 8,278,175 ("Cheng '175")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2007/0152266 ("Doyle")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 9,070,719

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 9,362,290

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 7,335,583 ("Chang")

Mar 19, 2019EXHIBITPETITIONER

File history for U.S. Patent No. 9,070,719

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2006/0024940 ("Furukawa")

Mar 19, 2019EXHIBITPETITIONER

H. Iwai, Roadmap for 22 nm and beyond, 86 Microelectronic Engineering, 1520-1528 (2009) ("Iwai")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2006/0175669 ("Kim")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 9,293,377 (the " '377 patent")

Mar 19, 2019EXHIBITPETITIONER

Chinese Patent No. 102956457B

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 7,531,437 ("Brask")

Mar 19, 2019EXHIBITPETITIONER

Mike Smayling, Gridded Design Rules-1 D Approach Enables Scaling of CMOS Logic, 6 Nanochip Technology Journal, 33-37 (2008) ("Nanochip Technology Journal")

Mar 19, 2019EXHIBITPETITIONER

Intel Technology Journal Vol. 12, Issue 2, 77-86, 121-130 (June 17, 2008) ("Intel Technology Journal")

Mar 19, 2019EXHIBITPETITIONER

Jack Kavalieros et al., Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, 2006 IEEE Symposium on VLSI Technology Digest of Technical Papers (2006) ("Kavalieros")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2011/0068411 ("Sun")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 6,413,802 ("Hu")

Mar 19, 2019EXHIBITPETITIONER

Mark Bohr and Kaizad Mistry, Intel's Revolutionary 22nm Transistor Technology, last visited August 27, 2018 ("Intel 22nm May 2011")

Mar 19, 2019EXHIBITPETITIONER

Brian Doyle et al., Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout, 2003 Symposium on VLSI Technology, Digest of Technical Papers 133-134 (2003) ("Doyle 2003")

Mar 19, 2019EXHIBITPETITIONER

WO International Patent Pub. No. 2008/114341 ("Okuno PCT (Japanese)")

Mar 19, 2019EXHIBITPETITIONER

EXPUNGED

Mar 19, 2019EXHIBITPETITIONER

Agilent Techs., Inc. v. Thermo Fisher Sci. Inc., IPR2018-00313, Paper 23 (PTAB June 18, 2018)

Mar 19, 2019EXHIBITPETITIONER

Stanley Wolf, Silicon Processing for the VLSI Era - Vol 4: Deep-Submicron Process Tech. 1-16, 181-226 (Lattice Press 2002) ("Wolf 2002")

Mar 19, 2019EXHIBITPETITIONER

Stanley Wolf, Silicon Processing for the VLSI Era - Vol 2: Process Integration 298-367 (Lattice Press 1990) ("Wolf 1990")

Mar 19, 2019EXHIBITPETITIONER

Michael Quirk & Julian Serda, Semiconductor Manufacturing Technology 21-42, 199-224, 257-298, 475-514, 634 (Prentice Hall 2001) ("Quirk")

Mar 19, 2019EXHIBITPETITIONER

Alan G. Lewis & John Y. Chen, VLSI ELECTRONICS MICROSTRUCTURE SCIENCE - Vol 18: Advanced MOS Device Physics 37-117 (Academic Press 1989) ("Lewis")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 4,234,362 ("Riseman")

Mar 19, 2019EXHIBITPETITIONER

Sang H. Dhong & Edward J. Petrillo, Sidewall Spacer Technology for MOS and Bipolar Devices, 133 J. Electrochem. Soc., 389-396 (Feb. 1986) ("Dhong")

Mar 19, 2019EXHIBITPETITIONER

Paul J. Tsang et al., Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology, 17 IEEE Journal of Solid-State Circuits, 220-226 (April 1982) ("Tsang")

Mar 19, 2019EXHIBITPETITIONER

Linda Geppert, The Amazing Vanishing Transistor Act, IEEE Spectrum, 28-33 (Oct. 2002) ("Geppert")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 7,524,727 ("Dewey")

Mar 19, 2019EXHIBITPETITIONER

K. Mistry et al., A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, 2007 International Electron Devices Meeting Tech. Dig. 247-250 (2007) ("Mistry")

Mar 19, 2019EXHIBITPETITIONER

A. Chatterjee et al., Sub-100nm Gate Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process, 1997 International Electron Devices Meeting Tech. Dig. 821-824 (Dec. 7-10, 1997) ("Chatterjee")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2007/0138559 ("Bohr")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 5,960,270 ("Misra")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 6,664,195 ("Jang")

Mar 19, 2019EXHIBITPETITIONER

Scott E. Thompson, et. al., A 90-nm Logic Technology Featuring Strained-Silicon, 51 IEEE Tran. Electron Devices, 1790-1797 (Nov. 2004) ("Thompson")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2011/0147831 ("Steigerwald")

Mar 19, 2019EXHIBITPETITIONER

S. Natarajan, et al., A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors Enhanced Channel Strain and 0.171µm2 SRAM Cell Size in a 291Mb Array, IEEE Electron Devices Meeting (2008) ("Natarajan")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent No. 7,838,373 ("Giles")

Mar 19, 2019EXHIBITPETITIONER

U.S. Patent Application Pub. No. 2007/0284671 ("Tsutsumi")

Mar 19, 2019EXHIBITPETITIONER

Z. Guo et al., FinFET-based SRAM design, Proceedings of the 2005 International Symposium on Low Power Electronics and Design 2-7 (2005) ("Guo")

Mar 19, 2019EXHIBITPETITIONER

S. C. Song et al., Systematic approach of FinFET based SRAM bitcell design for 32nm node and below, IEEE International Conference on IC Design and Technology ICICDT'09, 165-168 (2009) ("Song")

Mar 19, 2019EXHIBITPETITIONER

Kelin J. Kuhn et al., Process technology variation, IEEE Transactions on Electron Devices 58.8 (2011) 2197-2208 ("Kuhn")

Mar 19, 2019EXHIBITPETITIONER

Gen. Plastic Indus. Co. v. Canon Kabushiki Kaisha, IPR2016-01357, Paper 19 (PTAB Sept. 6, 2017)

Mar 19, 2019EXHIBITPETITIONER

Intel Corp. v. Alacritech, Inc., IPR2018-00226, Paper 7 (PTAB June 5, 2018)

Mar 19, 2019EXHIBITPETITIONER

K. Sukegawa et al., Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform, 2007 IEEE Symposium on VLSI Technology, 174-175 (2007) ("Sukegawa")

Mar 19, 2019EXHIBITPETITIONER

Badih El-Kareh, Silicon Devices and Process Integration, Deep Submicron and Nano-Scale Technologies, 439-446 (Springer 2009) ("El-Kareh")

Mar 19, 2019EXHIBITPETITIONER

Xuejue Huang et al., Sub 50-nm FinFET: PMOS, International Electron Devices Meeting, 67-70 (1999) ("Huang 1999")

Mar 19, 2019EXHIBITPETITIONER

Digh Hisamoto et al., A Folded-channel MOSFET for Deep-sub-tenth Micron Era, International Electron Devices Meeting, 1032-1034 (1998) ("Hisamoto")

Mar 19, 2019EXHIBITPETITIONER

Cheng-Tung Huang et al., New Negative-Bias-Temperature-Instability Improvement Using Buffer Layer, 46 Jpn. J. Appl. Phys., 2015-2018 (2007) ("Huang 2007")

Mar 19, 2019EXHIBITPETITIONER

Jakub Kedzierski et al., High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices, International Electron Devices Meeting, 437-440 (2001) ("Kedzierski")

Mar 19, 2019EXHIBITPETITIONER

Mayank Shrivastava et al., Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines, IEEE Transactions on Electron Devices, 1597-1607 (June 2011) ("Shrivastava")

Mar 19, 2019EXHIBITPETITIONER

Jean-Pierre Colinge, FinFETs and Other Multi-Gate Transistors, 49-111 (Springer 2008) ("Colinge")

Mar 19, 2019EXHIBITPETITIONER

2001 International Technology Roadmap for Semiconductors - Front End Processes, Semiconductor Industry Association (2001) ("2001 ITRS")

Mar 19, 2019EXHIBITPETITIONER

DECLARATION OF DR. SCOTT THOMPSON IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 9,070,719

Mar 19, 2019EXHIBITPETITIONER

PETITION FOR INTER PARTES REVIEW F U.S. PATENT NO. 9,070,719 B2 Claims 1-3, 6-7

Mar 19, 2019PAPERPETITIONER

Power of Attorney

Mar 19, 2019PAPERPETITIONER