Intel Corporation vs Tela Innovations, Inc.

Trial Instituted Document

PETITIONER¿¿¿S REASONS FOR PARALLEL PETITIONS AND PETITION RANKING

Patent Owner Sur-reply

PETITIONER'S REPLY FILED PURSUANT TO BOARD'S AUTHORIZATION

Subramanian ITC Witness Statement Excerpt

Hook ITC Rebuttal Witness Statement Excerpt

Board's 1-23-20 email authorizing reply

Tela 2002 - Complaint filed 05-15-18

Tela 2003 - First Amended Complaint filed 07-23-18

Tela 2004 - Order Denying Motion to Transfer Venue and Motions to Seal filed 09-18-18

Patent Owner Preliminary Response

Patent Owner Exhibit List 2

Tela 2006 - Tela Answer to First Amended Complaint filed 12-19-18

Tela 2011 - Stipulation and Order filed 11-15-18

Tela 2012 - Intel Contentions Exhibit 12-A Yano_012

Tela 2014 - Intel Contentions Exhibit 1-A Allen_012

Tela 2023 - Intel Contentions Exhibit 12-D Yano_523

Tela 2031 - Intel Contentions Exhibit 16-C Greenway_335

Tela 2035 - ITC Intel Fifth Supp Objections and Responses to Tela First Set of Irrog 1-68 (Part 1 of 2)

Tela 2036 - ITC Order No 6 filed 04-11-19

Tela 2037 - ITC Letter to Judge Barton dated 02-26-19

Tela 2007 - Second Amended Complaint filed 03-15-19

Tela 2008 - Intel Partial Answer filed 03-15-19

Tela 2009 - Intel Answer filed 06-27-19

Tela 2010 - Tela Answer to Second Amended Complaint filed 08-28-19

Tela 2013 - Intel Contentions Exhibit 8-A Kitabayashi_012

Tela 2015 - Intel Contentions Exhibit 5-A Ichiryu_012

Tela 2016 - Intel Contentions Exhibit 12-E Yano_966

Tela 2017 - Intel Contentions Exhibit 8-E Kitabayashi_966

Tela 2018 - Intel Contentions Exhibit 1-E Allen_966

Tela 2019 - Intel Contentions Exhibit 5-E Ichiryu_966

Tela 2020 - Intel Contentions Exhibit 7-D Chang_523

Tela 2021 - Intel Contentions Exhibit 8-D Kitabayashi_523

Tela 2022 - Intel Contentions Exhibit 20-D Maziasz_523

Tela 2024 - Intel Contentions Exhibit 6-D Ikoma_523

Tela 2025 - Intel Contentions Exhibit 7-D Intel Chang_352

Tela 2026 - Intel Contentions Exhibit 4-D IBM Chang_352

Tela 2027 - Intel Contentions Exhibit 8-D Kitabayashi_352

Tela 2028 - Intel Contentions Exhibit 25-B Becker_334

Tela 2029 - Intel Contentions Exhibit 16-B Greenway_334

Tela 2030 - Intel Contentions Exhibit 25-C Becker_335

Tela 2032 - Tela Amended Answer to First Amended Complaint filed 02-08-19

Tela 2033 - ITC Verified Amended Complaint filed 02-06-19

Tela 2034 - ITC Intel Response to Amended Complaint filed 04-02-19

Tela 2035 - ITC Intel Fifth Supp Objections and Responses to Tela First Set of Irrog 1-68 (Part 2 of 2)

Tela 2038 - McCarthy Declaration

Patent Owner Supplemental Mandatory Notice

Patent Owner Power of Attorney

ORDER - Granting Patent Owners Motions for Pro Hac Vice Admission of Andrew P. Zappia 37 C.F.R. 42.10(c)

Patent Owner Motion for Pro Hac Vice Admission of Andrew P. Zappia

TELA 2001 - Declaration of Andrew P. Zappia

Patent Owner Exhibit List 1

Notice of Accord Filing Date

Patent Owner Power of Attorney

Patent Owner Mandatory Notice

Petition for Inter Partes Review

Petitioner's Power of Attorney

Declaration of Dr. Stanley Shanfield

Curriculum Vitae of Dr. Stanley Shanfield

U.S. Patent No. 10,186,523

Backend CAD Flows for Restrictive Design Rules (Lavin)

U.S. Patent No. 7,503,026 (Ichiryu)

U.S. Patent No. 7,335,583 (Intel Chang)

U.S. Patent No. 7,465,973 (IBM Chang)

Declaration of Martin L. Knott in Support of Public Availability of VLSI Design Techniques for Analog and Digital Circuits (Geiger)

Excerpts from CMOS Circuit Design, Layout, and Simulation (Baker)

U.S. Provisional Patent Application No. 60/781,288

Excerpts from Analysis and Design of Digital Integrated Circuits (Hodges) (Part 1)

Excerpts from Analysis and Design of Digital Integrated Circuits (Hodges) (Part 2)

Excerpts from Microelectronic Circuits (Sedra) (Part 1)

Excerpts from Microelectronic Circuits (Sedra) (Part 2)

Excerpts from Microelectronic Circuits (Sedra) (Part 3)

Excerpts from Microchip Manufacturing (Wolf) (Part 1)

Excerpts from Microchip Manufacturing (Wolf) (Part 3)

Excerpts from VLSI Design Techniques for Analog and Digital Circuits (Geiger)

July 26, 2019 ITC Updated Joint Proposed Claim Construction Chart

June 13, 2019 NDCA Patent Local Rule 4-3 Joint Claim Construction and Prehearing Statement

U.S. Patent No. 4,682,202 (Tanizawa)

U.S. Patent Application No. 2006/0125024 (Ishigaki)

U.S. Patent No. 7,538,368 (Yano)

U.S. Patent No. 7,302,651 (Allen)

U.S. Patent No. 7,200,831 (Kitabayashi)

U.S. Patent No. 7,279,727 (Ikoma)

U.S. Patent No. 6,534,805 (Jin)

Declaration of Martin L. Knott in Support of Public Availability of Analysis and Design of Digital Integrated Circuits (Hodges)

Declaration of Martin L. Knott in Support of Public Availability of Layout Minimization of CMOS Cells (Maziasz)

Excerpts from Manufacturing-Aware Physical Design (Gupta)

Excerpts from Digital Integrated Circuits: A Design Perspective (Rabaey)

Excerpts from Layout Minimization of CMOS Cells (Maziasz)

Excerpts from Microchip Manufacturing (Wolf) (Part 2)

U.S. Patent No. 6,787,469 (Houston)

Declaration of Rachel J. Watters in Support of Public Availability of Microelectronic Circuits (Sedra)

Declaration of Gerard P. Grenier in Support of Public Availability of Manufacturing-Aware Physical Design (Gupta)

Declaration of Gerard P. Grenier in Support of Public Availability of Backend CAD Flows for Restrictive Design Rules (Lavin)

Excerpts from Computer Aids for VLSI Design (Rubin)

U.S. Patent No. 6,690,206 (Rikino)

U.S. Patent No. 6,034,433 (Beatty)

Declaration of Pamela Stansbury in Support of Public Availability of Computer Aids for VLSI Design (Rubin)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 1)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 2)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 3)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 4)

Declaration of Martin L. Knott in Support of Public Availability of Digital Integrated Circuits: A Design Perspective (Rabaey)

Excerpt from New Oxford American Dictionary (2d ed. 2005)

Excerpt from Wiley Electrical and Electronics Engineering Dictionary (2004)

337-TA-873 Joint List of Proposed Claim Constructions

U.S. Patent No. 6,396,087 (Kitabayashi ¿¿¿083 Patent)

Certified File History of U.S. Patent Application No. 13/774,940 (without copies of the prior art references)

U.S. Patent No. 7,079,413 (Tsukamoto)

EXPUNGED

Certified File History of U.S. Patent No. 10,186,523 (Part 3)

Certified File History of U.S. Patent No. 10,186,523 (Part 4)

Certified File History of U.S. Patent No. 10,186,523 (Part 1)

Certified File History of U.S. Patent No. 10,186,523 (Part 2)

Certified File History of U.S. Patent No. 10,186,523 (Part 9)

Certified File History of U.S. Patent No. 10,186,523 (Part 10)

Certified File History of U.S. Patent No. 10,186,523 (Part 11)

Certified File History of U.S. Patent No. 10,186,523 (Part 12)

Certified File History of U.S. Patent No. 10,186,523 (Part 13)

Certified File History of U.S. Patent No. 10,186,523 (Part 14)

Certified File History of U.S. Patent No. 10,186,523 (Part 16)

Certified File History of U.S. Patent No. 10,186,523 (Part 17)

Certified File History of U.S. Patent No. 10,186,523 (Part 5)

Certified File History of U.S. Patent No. 10,186,523 (Part 6)

Certified File History of U.S. Patent No. 10,186,523 (Part 7)

Certified File History of U.S. Patent No. 10,186,523 (Part 15)

Certified File History of U.S. Patent No. 10,186,523 (Part 18)

Certified File History of U.S. Patent No. 10,186,523 (Part 8)