Intel Corporation vs Tela Innovations, Inc.

Trial Certificate Checklist

Termination Decision Document

ORDER Granting Patent Owner's First Revised and Second Motions to Seal Denying Patent Owner's Third Motion to Seal Granting Petitioner's Motions to Seal

Hearing Transcript

Patent Owner's Reply to Petitioner's Opposition to Motion to Exclude

Patent Owner's Exhibit List 6

Patent Owner's Demonstrative Exhibit for Oral Argument

ORAL ARGUMENT DEMONSTRATIVES [SEALED]

PETITIONER'S MOTION TO SEAL ORAL ARGUMENT DEMONSTRATIVES

ORAL ARGUMENT DEMONSTRATIVES [PUBLIC REDACTED VERSION]

PETITIONER'S OPPOSITION TO PATENT OWNER'S MOTION TO EXCLUDE

Patent Owner's Motion to Exclude

Motion to Seal Patent Owner's Motion to Exclude

Order Trial Hearing

PETITIONER'S REQUEST FOR ORAL ARGUMENT

Patent Owner's Request for Oral Argument

Patent Owner's Sur-reply_PUBLIC REDACTED VERSION

Patent Owner's Sur-reply_HCONF_POM

Patent Owner's Exhibit List 5

EX2120 Shanfield Transcript Sept 30 2020

Patent Owner's Motion to Seal Sur-reply

Patent Owner's Second Notice of Deposition of Stanley Shanfield, Ph.D.

PUBLIC REDACTED VERSION - December 9, 2019 Trial Transcript (ITC Inv. No. 337-1148)

PUBLIC REDACTED VERSION - August 7, 2019 Deposition Transcript of Dhrumil Ghandi (ITC Inv. No. 337-TA-1148)

PUBLIC REDACTED VERSION - Tela Presentation

PUBLIC REDACTED VERSION - PETITIONER'S REPLY TO PATENT OWNER'S RESPONSE TO PETITION

PUBLIC REDACTED VERSION - DECLARATION OF STANLEY SHANFIELD, PH.D.

PUBLIC REDACTED VERSION - July 8, 2020 Deposition Transcript of Scott Becker (IPR2019-01228, IPR2019-1255)

PUBLIC REDACTED VERSION - Excerpt from October 22, 2019 Witness Statement of Christopher Auth, Ph.D.(ITC Inv. No. 337-TA-1148)

PUBLIC REDACTED VERSION - Tela and TSMC Intellectual Property Rights Agreement

PUBLIC REDACTED VERSION - Intel Market Share Data

PUBLIC REDACTED VERSION - Tela Innovations Business Plan Summary

Patent Owner's Objections to Evidence Submitted With Petitioner's Reply

MOTION FOR ENTRY OF PROPOSED PROTECTIVE ORDER AND TO SEAL

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Excerpt from Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

August 27, 2020 Deposition Transcript of Sunil P. Khatri, Ph.D.

December 9, 2019 Trial Transcript, ITC Investigation No. 337-TA-1148

July 8, 2020 Deposition Transcript of Scott Becker, IPR2019-01228 and IPR2019-01255

Tela Presentation

July 1, 2020 Deposition Transcript of Sunil Khatri, Ph.D., IPR2019-01228 and IPR2019-01255

Layout rule trends and effect upon CPU design

August 7, 2019 Deposition Transcript of Dhrumil Ghandi, ITC Investigation No. 337-TA-1148

Excerpt from October 22, 2019 Witness Statement of Christopher Auth, Ph.D., ITC Investigation No. 337-TA-1148

Gridded Design Rules ¿¿¿ 1-D Approach Enables Scaling of CMOS Logic

Intel Market Share Data

Tela Innovations Business Plan Summary

Tela and TSMC Intellectual Property Rights Agreement

Intel First to Demonstrate Working 45 nm Chips

PETITIONER'S REPLY TO PATENT OWNER'S RESPONSE TO PETITION

Declaration of Dr. Stanley Shanfield in Support of Petitioner¿¿¿s Reply to Patent Owner's Response

Petitioner's Updated Power of Attorney

Petitioner's Supplemental Mandatory Notice

Revised Motion for Entry of Proposed Protective Order and to Seal

THIRD JOINT STIPULATION EXTENDING DUE DATES 2-3

PETITIONER'S NOTICE OF DEPOSITION OF SUNIL P. KHATRI, PH.D.

Patent Owner¿¿¿s Response_PUBLIC REDACTED VERSION

EX2043 NDAs_PUBLIC REDACTED VERSION

EX2045 CX-1365C_PUBLIC REDACTED VERSION

EX2047 CX-1363C_PUBLIC REDACTED VERSION

EX2051 CX-1300C_PUBLIC REDACTED VERSION

EX2057 Tela A Fresh Approach to SoC Design__PUBLIC REDACTED VERSION

EX2040 Becker Decl_PUBLIC REDACTED VERSION

EX2044 CX-1364C_PUBLIC REDACTED VERSION

EX2046 CX-1366C_PUBLIC REDACTED VERSION

EX2048 CX-1361C_PUBLIC REDACTED VERSION

EX2049 CX-1360C_PUBLIC REDACTED VERSION

EX2052 CX-1301C_PUBLIC REDACTED VERSION

EX2053 CX-1302C_PUBLIC REDACTED VERSION

EX2054 CX-1303C_PUBLIC REDACTED VERSION

EX2055 CX-1298C_PUBLIC REDACTED VERSION

EX2056 CX-1299C_PUBLIC REDACTED VERSION

EX2058 Tela Innovative Design Solutions_PUBLIC REDACTED VERSION

EX2059 Intel Update 12.20.06_PUBLIC REDACTED VERSION

EX2060 TELAITC114800169754__PUBLIC REDACTED VERSION

EX2073 License Agreement_PUBLIC REDACTED VERSION

EX2098 14nm 523 Claim Chart Appx 1J_PUBLIC REDACTED VERSION

EX2099 10nm 523 Claim Chart Appx 1K_PUBLIC REDACTED VERSION

EX2101 Appx B Subramanian ITC Expert Report_PUBLIC REDACTED VERSION

EX2061 CX-0166C_PUBLIC REDACTED VERSION

Patent Owner Supplemental Mandatory Notice

Patent Owner's Exhibit List 4

EX2040 Becker Decl_HCONF_POM

EX2043 NDAs_POM

EX2044 CX-1364C_HCONF

EX2045 CX-1365C_HCONF

EX2046 CX-1366C_HCONF

EX2047 CX-1363C_HCONF

EX2048 CX-1361C_HCONF

EX2051 CX-1300C_HCONF_Part2of2

EX2056 CX-1299C_POM

EX2058 Tela Innovative Design Solutions_POM

EX2059 Intel Update 12.20.06_POM

EX2060 TELAITC114800169754_POM

Patent Owner's Response_HCONF_POM_OCR SOURCE CODE

EX2041 Patent Power 2012

EX2042 Interactive Patent Power 2012

EX2049 CX-1360C_HCONF

EX2050 CX-1048

EX2051 CX-1300C_HCONF_Part1of2

EX2052 CX-1301C_HCONF

EX2053 CX-1302C_HCONF

EX2054 CX-1303C_HCONF

EX2055 CX-1298C_HCONF

EX2057 Tela A Fresh Approach to SoC Design_POM

EX2061 CX-0166C_POM

EX2064 Intel 2018 Form 10-K

EX2065 Intel Just Put Mobile Processor Competitors On Notice

EX2067 Intel Launches First 14-nanometre Processor

EX2068 Intels New Core M Chips

EX2063 Intel 2014 Form 10-K

EX2066 Intel Moores Law Still Ticking

EX2069 Intel.com Altera to Build FPGAs

EX2070 Intel.com Cadence and Intel Collaborate

EX2072 Intel.com Intel Discloses Newest Microarchitecture

EX2073 License Agreement_HCONF

EX2074 Khatri Decl_HCONF_POM_OCR SOURCE CODE

EX2077 Kang CMOS Digital Integrated Circuits

EX2079 Bohr Technology Leadership

EX2085 Intel.com Intel 14nm Technology

EX2088 Brain 14nm Technology Leadership

EX2071 Intel.com Synopsys and Intel Collaborate

EX2075 Khatri CV

EX2076 Weste CMOS VLSI Design

EX2078 Bohr 14nm Process Technology

EX2086 Intel.com Making Silicon Chips

EX2087 Intel White Paper Introduction to Intel Architecture

EX2089 Intel.com Intel 22nm Technology

EX2096 May 22 2020 ITC Decision

EX2093 CAND 18-2848 Claim Construction Order

EX2099 10nm 523 Claim Chart Appx 1K_OCR SOURCE CODE

EX2101 Appx B Subramanian ITC Expert Report_OCR SOURCE CODE

EX2103 IEDM 2014 Preview

EX2105 Intel 2019 Form 10-K

EX2097 Shanfield Transcript June 23 2020

EX2098 14nm 523 Claim Chart Appx 1J_OCR SOURCE CODE

EX2100 Joint Stipulation re Product Sales

EX2102 Bohr Continuing Moores Law

EX2104 Intels 14nm Broadwell chip reverse engineered

EX2106 Kaizad Mistry 10nm Tech Leadership

EX2107 Intel Core i3-8121U Processor

EX2109 GDs2Mesh 3D TCAD model construction tool

EX2108 Intel Responses to 1st Interrogatories

EXPUNGED

EX2117 Proposed Protective Order

Patent Owner's Supplemental Mandatory Notice (Shifton)

Patent Owner's Power of Attorney (Shifton)

Patent Owner's Notice of Deposition of Stanley Shanfield, Ph.D.

Second Joint Stipulation Extending Due Dates 1-2

Granting Patent Owners Motions for Pro Hac Vice Admission of Christina L. Shifton 37 C.F.R. sec 42.10(c)

Patent Owner's Exhibit List 3

Patent Owner's Motion for Pro Hac Vice Admission for Christina L. Shifton Under 37 C.F.R. 42.10

Declaration of Christina L. Shifton in Support of Patent Owner's Motion for Pro Hac Vice Admission

ORDER Granting Patent Owner¿¿¿s Motion for Additional Discovery 37 C.F.R. ¿¿ 42.51(b)(2)

JOINT STIPULATION EXTENDING DUE DATE 1

PETITIONER'S OPPOSITION TO PATENT OWNER'S MOTION FOR LIMITED DISCOVERY FROM PETITIONER REGARDING OBJECTIVE EVIDENCE OF NON-OBVIOUSNESS

4-3-20 Telephonic Conference Transcript

EXPUNGED

EXPUNGED

EXPUNGED

EXPUNGED

Patent Owner Motion for Limited Discovery from Petitioner Regarding Objective Evidence of Non-Obviousness

ORDER Conduct of the Proceeding 37 C.F.R. sec 42.5

Patent Owner's Objections to Evidence Submitted Prior to Institution

Patent Owner Power of Attorney

Patent Owner Power of Attorney

Patent Owner Supplemental Mandatory Notice

Decision - Granting Institution of Inter Partes Review

Scheduling Order

Granting Patent Owner's Motions for Pro Hac Vice Admission of Andrew P. Zappia 37 C.F.R. sec. 42.10(c)

Patent Owner Sur-reply

Subramanian ITC Witness Statement Excerpt

PETITIONER'S REPLY FILED PURSUANT TO BOARD'S AUTHORIZATION

Board¿¿¿s 12-27-19 email authorizing reply

Hook ITC Rebuttal Witness Statement Excerpt

Patent Owner Preliminary Response

Patent Owner Exhibit List 2

Tela 2002 - Complaint filed 05-15-18

Tela 2004 - Order Denying Motion to Transfer Venue and Motions to Seal filed 09-18-18

Tela 2005 - Transcript of Proceedings held 10-03-18

Tela 2006 - Tela Answer to First Amended Complaint filed 12-19-18

Tela 2007 - Second Amended Complaint filed 03-15-19

Tela 2008 - Intel Partial Answer filed 03-15-19

Tela 2003 - First Amended Complaint filed 07-23-18

Tela 2009 - Intel Answer filed 06-27-19

Tela 2010 - Tela Answer to Second Amended Complaint filed 08-28-19

Tela 2017 - Intel Contentions Exhibit 8-E Kitabayashi_966

Tela 2020 - Intel Contentions Exhibit 7-D Chang_523

Tela 2024 - Intel Contentions Exhibit 6-D Ikoma_523

Tela 2011 - Stipulation and Order filed 11-15-18

Tela 2012 - Intel Contentions Exhibit 12-A Yano_012

Tela 2013 - Intel Contentions Exhibit 8-A Kitabayashi_012

Tela 2014 - Intel Contentions Exhibit 1-A Allen_012

Tela 2015 - Intel Contentions Exhibit 5-A Ichiryu_012

Tela 2016 - Intel Contentions Exhibit 12-E Yano_966

Tela 2018 - Intel Contentions Exhibit 1-E Allen_966

Tela 2019 - Intel Contentions Exhibit 5-E Ichiryu_966

Tela 2021 - Intel Contentions Exhibit 8-D Kitabayashi_523

Tela 2022 - Intel Contentions Exhibit 20-D Maziasz_523

Tela 2023 - Intel Contentions Exhibit 12-D Yano_523

Tela 2025 - Intel Contentions Exhibit 7-D Intel Chang_352

Tela 2026 - Intel Contentions Exhibit 4-D IBM Chang_352

Tela 2027 - Intel Contentions Exhibit 8-D Kitabayashi_352

Tela 2028 - Intel Contentions Exhibit 25-B Becker_334

Tela 2029 - Intel Contentions Exhibit 16-B Greenway_334

Tela 2031 - Intel Contentions Exhibit 16-C Greenway_335

Tela 2032 - Tela Amended Answer to First Amended Complaint filed 02-08-19

Tela 2033 - ITC Verified Amended Complaint filed 02-06-19

Tela 2034 - ITC Intel Response to Amended Complaint filed 04-02-19

Tela 2036 - ITC Order No 6 filed 04-11-19

Tela 2037 - ITC Letter to Judge Barton dated 02-26-19

Tela 2038 - McCarthy Declaration

Tela 2030 - Intel Contentions Exhibit 25-C Becker_335

Tela 2035 - ITC Intel Fifth Supp Objections and Responses to Tela First Set of Irrog 1-68 (Part 1 of 2)

Tela 2035 - ITC Intel Fifth Supp Objections and Responses to Tela First Set of Irrog 1-68 (Part 2 of 2)

Patent Owner Motion for Pro Hac Vice Admission of Andrew P. Zappia

TELA 2001 - Declaration of Andrew P. Zappia

Patent Owner Exhibit List 1

NOTICE OF FILING DATE ACCORDED TO PETITION AND TIME FOR FILING PATENT OWNER PRELIMINARY RESPONSE

Patent Owner Mandatory Notice

Patent Owner Power of Attorney

Petitioner's Power of Attorney

Petition for Inter Partes Review

U.S. Patent No. 10,186,523

July 26, 2019 ITC Updated Joint Proposed Claim Construction Chart

June 13, 2019 NDCA Patent Local Rule 4-3 Joint Claim Construction and Prehearing Statement

U.S. Patent No. 4,682,202 (Tanizawa)

Declaration of Dr. Stanley Shanfield

Curriculum Vitae of Dr. Stanley Shanfield

U.S. Provisional Patent Application No. 60/781,288

U.S. Patent No. 7,538,368 (Yano)

U.S. Patent No. 7,302,651 (Allen)

U.S. Patent No. 7,335,583 (Intel Chang)

U.S. Patent No. 7,465,973 (IBM Chang)

U.S. Patent No. 7,200,831 (Kitabayashi)

U.S. Patent No. 7,279,727 (Ikoma)

U.S. Patent No. 6,534,805 (Jin)

Declaration of Martin L. Knott in Support of Public Availability of VLSI Design Techniques for Analog and Digital Circuits (Geiger)

Excerpts from CMOS Circuit Design, Layout, and Simulation (Baker)

Excerpts from Manufacturing-Aware Physical Design (Gupta)

Excerpts from Analysis and Design of Digital Integrated Circuits (Hodges) (Part 2)

Excerpts from Digital Integrated Circuits: A Design Perspective (Rabaey)

Excerpts from Microelectronic Circuits (Sedra) (Part 2)

Excerpts from Microelectronic Circuits (Sedra) (Part 3)

Excerpts from Layout Minimization of CMOS Cells (Maziasz)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 1)

U.S. Patent Application No. 2006/0125024 (Ishigaki)

Backend CAD Flows for Restrictive Design Rules (Lavin)

U.S. Patent No. 7,503,026 (Ichiryu)

Declaration of Martin L. Knott in Support of Public Availability of Analysis and Design of Digital Integrated Circuits (Hodges)

Declaration of Martin L. Knott in Support of Public Availability of Layout Minimization of CMOS Cells (Maziasz)

Excerpts from Analysis and Design of Digital Integrated Circuits (Hodges) (Part 1)

Excerpts from Microelectronic Circuits (Sedra) (Part 1)

Excerpts from Microchip Manufacturing (Wolf) (Part 1)

Excerpts from Microchip Manufacturing (Wolf) (Part 2)

Excerpts from Microchip Manufacturing (Wolf) (Part 3)

U.S. Patent No. 6,787,469 (Houston)

Excerpts from VLSI Design Techniques for Analog and Digital Circuits (Geiger)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 3)

Declaration of Rachel J. Watters in Support of Public Availability of Microelectronic Circuits (Sedra)

Declaration of Gerard P. Grenier in Support of Public Availability of Backend CAD Flows for Restrictive Design Rules (Lavin)

Declaration of Martin L. Knott in Support of Public Availability of Digital Integrated Circuits: A Design Perspective (Rabaey)

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 2)

Declaration of Gerard P. Grenier in Support of Public Availability of Manufacturing-Aware Physical Design (Gupta)

337-TA-873 Joint List of Proposed Claim Constructions

U.S. Patent No. 6,396,087 (Kitabayashi ¿¿¿083 Patent)

Declaration of Pamela Stansbury in Support of Public Availability of Computer Aids for VLSI Design (Rubin)

Excerpt from New Oxford American Dictionary (2d ed. 2005)

Excerpt from Wiley Electrical and Electronics Engineering Dictionary (2004)

Certified File History of U.S. Patent Application No. 13/774,940 (without copies of the prior art references)

Excerpts from Computer Aids for VLSI Design (Rubin)

U.S. Patent No. 7,079,413 (Tsukamoto)

U.S. Patent No. 6,690,206 (Rikino)

U.S. Patent No. 6,034,433 (Beatty)

Petitioner's Reasons for Parallel Petitions and Petition Ranking

Declaration of Dr. James L. Mullins in Support Public Availability of CMOS Circuit Design, Layout, and Simulation (Baker) and Microchip Manufacturing (Wolf) (Part 4)

Certified File History of U.S. Patent No. 10,186,523 (Part 1)

Certified File History of U.S. Patent No. 10,186,523 (Part 2)

Certified File History of U.S. Patent No. 10,186,523 (Part 4)

Certified File History of U.S. Patent No. 10,186,523 (Part 5)

Certified File History of U.S. Patent No. 10,186,523 (Part 6)

Certified File History of U.S. Patent No. 10,186,523 (Part 11)

Certified File History of U.S. Patent No. 10,186,523 (Part 12)

Certified File History of U.S. Patent No. 10,186,523 (Part 15)

Certified File History of U.S. Patent No. 10,186,523 (Part 16)

Certified File History of U.S. Patent No. 10,186,523 (Part 10)

Certified File History of U.S. Patent No. 10,186,523 (Part 13)

Certified File History of U.S. Patent No. 10,186,523 (Part 17)

Certified File History of U.S. Patent No. 10,186,523 (Part 18)

Certified File History of U.S. Patent No. 10,186,523 (Part 8)

Certified File History of U.S. Patent No. 10,186,523 (Part 9)

Certified File History of U.S. Patent No. 10,186,523 (Part 7)

Certified File History of U.S. Patent No. 10,186,523 (Part 14)

Certified File History of U.S. Patent No. 10,186,523 (Part 3)