Advanced Micro Devices, Inc. et al. vs Monterey Research, LLC et al.

Other: other court decision

Other: Fed Circuit mandate

Patent Owner's Notice of Appeal

Final Written Decision: original

Other: Hearing transcript

Patent Owner's Demonstratives

Petitioner's Updated Table of Exhibits

Petitioner's Demonstratives

EXPUNGED

EXPUNGED

Petitioner Advanced Micro Devices, Inc.'s Updated Mandatory Notices Pursuant to 37 C.F.R 42.8(a)(2)

Granting Requests for Oral Argument 37 C.F.R. sec. 42.70

Petitioner's Request for Oral Argument

MRL's Request for Oral Argument

Order - Denying Patent Owner's Motion to Strike - 37 CFR 42.5

AMD's Opposition to Patent Owner Motion to Strike Publication Evidence

Ex. 2014

Ex. 2015

Ex. 2016

Ex. 2017

Ex. 2018

Ex. 2019

Ex. 2020

MRL Sur-Reply

Granting Institution of Inter Partes Review 35 U.S.C. sec. 314 Granting Motion for Joinder 35 U.S.C. sec. 315(c); 37 C.F.R. sec. 42.122

MRL's Motion to Strike

Patent Owner's Notice of Deposition of Dr. Hatalis

Patent Owner's Objections to Evidence

Petitioner Advanced Micro Devices, Inc.'s Updated Mandatory Notices Pursuant to 37 C.F.R. 42.8(a)(2)

Petitioner Advanced Micro Devices, Inc.'s Updated Power of Attorney

Reply In Support of Petition for Inter Partes Review of U.S. Patent No. 6,534,805

Pi, Jen-I, MOSIS Scaleable CMOS Design Rules (revision 7), pp. 1-28, Aug. 1, 1995

Singh, et al., MorphoSys: A Reconfigurable Architecture for Multimedia Applications, IEEE Xplore, pp. 134-139 (1998)

Lee et al., Design and Implementation of the MorphoSys Reconfigurable Computing Processor, J. of VLSI Signal Processing Systems, 2:147-164 (2000)

Stephen A. Campbell, The Science And Engineering of Microelectronic Fabrication, 427-439 (Oxford University Press, 1996)

Declaration of Debra L. Tasker (dated Mar. 12, 2021) with Exs. A and B. (cover, title and copyright pages, pp. 876-877, and inside back cover of CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker)

Declaration of Rebecca MacKay Johnson (dated Mar. 15, 2021) regarding CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker

Robert F. Pierret, Semiconductor Device Fundamentals, 611-620 (Addison-Wesley Publishing Company, 1996)

Purdue MARC source record

Declaration of Nathan Rupp (dated Mar. 16, 2021) regarding CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker

Scheffler et al., On the Impact of Design Rules To High-Density Substrate Yield, Proceedings IMAPS Europe 2000 (June 18-20, 2000)

Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 47-50 (Kluwer Academic Publishers 1993)

The University of Texas at Tyler Libraries catalog ��� MARC details for CMOS circuit design, layout, and simulation (Record no. 119771)

U.S. Patent No. 5,824,579

U.S. Patent No. 6,169,313

U.S. Patent No. 6,418,551

U.S. Patent No. 6,681,376

Peter Van Zant, Microchip Fabrication, 502-510, (3rd Ed. McGraw Hill, 1997)

Declaration of Rachel Watters (dated Mar. 16, 2021) with Ex. A. (cover, title and copyright pages, pg. 877, and inside back cover of CMOS Circuit Design, Layout, and Simulation by R. Jacob Baker)

Reply Declaration of Dr. Gretchen Hoffman In Support of Advanced Micro Devices, Inc.���s Petition for Inter Partes Review of U.S. Patent No. 6,534,805, dated May 28, 2021

Expert Declaration of Dr. R. Jacob Baker In Support of Advanced Micro Devices, Inc.'s Petition of Inter Partes Review of U.S. Patent No. 6,534,805

Reply Declaration of Dr. Miltiadis Hatalis In Support of Advanced Micro Devices, Inc.'s Petition for Inter Partes Review of U.S. Patent No. 6,534,805, dated June 3, 2021

Deposition Transcript of Nader Bagherzadeh, Ph.D, dated April 30, 2021

David J. Elliot, Integrated Circuit Fabrication Technology, Ch. 1 (pp. 1-9) and Ch. 2 (pp. 43-49) (McGraw-Hill Book Company, 1982)

M. Michael Vai, Ph.D, VLSI Design, Ch. 1 (pp. 1-4) (CRC Press, 2001)

S.M. Sze, VLSI Technology, Ch. 4 (pp. 141-143) (2nd Ed., McGraw-Hill Book Company, 1988)

Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication, Ch. 7 (pp. 151-153) (2nd Ed., Oxford University Press, 2001)

Carver Mead and Lynn Conway, Introduction to VLSI Systems, 47-51 (Addison-Wesley Publishing Company, 1980)

Inohara et al., Highly Scalable and Fully Logic Compatible SRAM Cell Technology with Metal Damascene Process and W Local Interconnect, IEEE, pp. 64-65 (1998)

Petitioner AMD's Notice of Deposition of Dr. Nader Bagherzadeh

Corrected Patent Owner's Response

Ex. 2004

Ex. 2006

Ex. 2007

Ex. 2008

Ex. 2009

Ex. 2010

Ex. 2011

Ex. 2012

Ex. 2013

Ex. 2005

MRL Response

Stipulation to Modify Due Dates 1-2

Stipulation to Change Due Dates 1-3

Granting Patent Owners Unopposed Motion for Pro Hac Vice Admission of Eliyahu Balsam 37 C.F.R. sec 42.10

Mandatory Notices

Motion to Appear Pro Hac Vice

Ex.. 2003

Revised Deposition Notice for Dr. Baker

Deposition Notice for Dr. Hatalis

Deposition Notice for Dr. Hoffman

Deposition Notice for Dr. Baker

Stipulation to Change Due Dates 1-3

Trial Instituted Document

Scheduling Order

Updated Mandatory Notices

Ex. 2001

Ex. 2002

Patent Owner Preliminary Response

MLR's 990 Updated Power of Attorney

MRL's 990 Updated Mandatory Notices

MRL's 990 Updated Mandatory Notices

MRL's 990 Power of Attorney

MRL's 990 Mandatory Notices

Notice of Accord Filing Date

Petitioner's Certification of Word Count

U.S. Patent No. 6,417,549 ("Oh")

Petition for Inter Partes Review of U.S. Patent No. 6,534,805

Petitioner Advanced Micro Devices, Inc.'s Power of Attorney

U.S. Patent No. 6,534,805 (with Ex Parte Reexamination Certificate Appended)

Declaration of Dr. Miltiadis Hatalis

Curriculum Vitae of Dr. Miltiadis Hatalis

Prosecution History for U.S. Patent Application No. 09/829,510

Ex Parte Reexamination History for U.S. Patent No. 6,534,805 Part 1 of 4

Ex Parte Reexamination History for U.S. Patent No. 6,534,805 Part 2 of 4

R. JACOB BAKER ET AL., CMOS CIRCUIT DESIGN, LAYOUT AND SIMULATION, IEEE Press (1998) ("CMOS Circuit Design")

Ex Parte Reexamination History for U.S. Patent No. 6,534,805 Part 3 of 4

Ishida, et al., "A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns Scalable beyond 0.18 um Generation and Desirable for Ultra High Speed Operation," IEDM 98, IEEE 1998, pp. 201-204 ("Ishida IEDM")

U.S. Patent No. 6,677,649 ("Osada")

Certain Static Random Access Memories and Products Containing the Same, USITC Inv. No. 337-TA-792, Order 29 (Feb. 9, 2012)

IEEE Press Royalty Statement for CMOS Circuit Design

Declaration of Dr. Gretchen Hoffman

Curriculum Vitae of Dr. Gretchen Hoffman

Machine Readable Cataloging ("MARC") Bibliographic Record for CMOS Circuit Design (University of North Texas Library)

Ex Parte Reexamination History for U.S. Patent No. 6,534,805 Part 4 of 4

Declaration of Dr. Jacob Baker

Machine Readable Cataloging ("MARC") Bibliographic Record for CMOS Circuit Design (OCLC)

Machine Readable Cataloging ("MARC") Bibliographic Record for CMOS Circuit Design (University of Texas Library)

Machine Readable Cataloging ("MARC") Bibliographic Record for CMOS Circuit Design (North Carolina State University Library)