Xilinx, Inc. vs ARBOR GLOBAL STRATEGIES LLC,

Other: other court decision

Other: Fed Circuit mandate

Patent Owner's Notice of Appeal

Final Written Decision: original

Other: Hearing transcript

Petitioner's Demonstratives

Petitioner's Updated Exhibit List

Patent Owner's Updated Exhibit List

Ex. 2016 - Patent Owner's Demonstratives

Other: Order Granting Petitioner and Patent Owner Requests for Oral Argument

Patent Owner's Request for Oral Argument

Request for Oral Argument

Patent Owner's Sur-Reply

Order: Authorizing Deposition Exhibit

Patent Owner's Notice of Deposition of Paul Franzon, Ph.D.

Notice of Stipulation to Modify Due Date 3

Supplemental Declaration of Dr. Paul Franzon, Ph.D.

Chart of Arbor���s Various Positions Re: ���memory���accelerate������ Terms

Arbor Global Strategies LLC���s Opening Claim Construction Brief

Arbor Global Strategies LLC���s Reply Claim Construction Brief

Affidavit of Arbor���s Expert Dr. Robert Darveaux (September 29, 2020) in support of Arbor���s Claim Construction Brief

Deposition Transcript of Arbor���s Expert Dr. Krishnendu Chakrabarty (May 5, 2021) in IPR2020-01020, -01021, and -01022 (Part 1)

Deposition Transcript of Arbor���s Expert Dr. Krishnendu Chakrabarty (May 5, 2021) in IPR2020-01020, -01021, and -01022 (Part 2)

Deposition Transcript of Arbor���s Expert Dr. Shukri J. Souri (August 13, 2021) in IPR2020-01567, -01568, -01570, and 0-1571

Excerpt of Arbor���s Infringement Contentions

Arbor���s Patent Owner Response in IPR2020-01022

Arbor���s Patent Owner Sur-Reply in IPR2020-01022

Arbor���s Patent Owner Response in IPR2020-01021

Arbor���s Patent Owner Sur-Reply in IPR2020-01021

R. Scrofano, et al. "Energy efficiency of FPGAs and programmable processors for matrix multiplication"

U.S. Patent No. 5,056,012 to Spiotta

Petitioner's Reply

Petitioner's Notice of Deposition of Shukri J. Souri, Ph.D

Petitioners Objections to Evidence

DECISION Granting Institution of Inter Partes Review 35 U.S.C. �� 314 Granting Motion for Joinder 35 U.S.C. �� 315(c); 37 C.F.R. �� 42.122

Ex. 2011

Ex. 2012

Ex. 2013

Ex. 2014

Ex. 2015

Patent Owner's Response

Notice of Stipulation to Modify Due Dates 1 & 2

Patent Owner's Notice of Deposition of Paul Franzon, PH.D.

Patent Owner's Objections to Evidence

AMENDED SCHEDULING ORDER

DECISION Granting Institution of Inter Partes Review 35 U.S.C. § 314

SCHEDULING ORDER

Petitioner's Updated Mandatory Notices

Order Granting Petitioner's Unopposed Motions for Pro Hac Vice Admission of Jeffrey Shneidman

Order - Conduct of the Proceeding

Ex. 2008

Patent Owner's Preliminary Response

Ex. 2005

Ex. 2007

Petitioner's Unopposed Motion for Pro Hac Vice Admission of Jeffrey Shneidman

Declaration of Jeffrey Shneidman

Patent Owner's Power of Attorney

Patent Owner's Mandatory Notice

Patent Owner's Power of Attorney

Patent Owner's Mandatory Notice

Notice of Accord Filing Date

Silviu M. S. A. Chiricescu and M. Michael Vai, A Three-Dimensional FPGA with an Integrated Memory for In-Application Reconfiguration Data, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, May 1998, Print ISBN 0-7803-4455-3

Yoichi Akasaka, Three-Dimensional IC Trends, Proceedings of the IEEE, Vol. 74, Iss. 12, pp. 1703-1714, Dec. 1986, Print ISSN 0018-9219

PCT Application Publication No. WO00/62339 to Satoh

Declaration of Mr. Jacob Munford Part 1

Declaration of Mr. Jacob Munford Part 2

File Wrapper of the 214 Patent

File Wrapper of US 6,627,985

Complaint in Arbor Global Strategies v. Samsung, 19-cv-00333 (E.D. Texas) D.I. 1

Said F. Al-sarawi, Derek Abbott, and Paul D. Franzon, A Review of 3-D Packaging Technology, Proceedings of the 1998 IEEE Transactions on Components, Packaging, and Manufacturing Technology, February 1998, PII S 1070-9894(98)00595-7

Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, and Katsuyuki Sakuma, Future System-on-silicon LSI Chips, IEEE 1998

U.S. Patent No. 7,126,214 to Huppenthal

Steve Trimberger, Dean Carberry, Anders Johnson, and Jennifer Wong, A Time-Multiplexed FPGA, Proceedings of the 1997 IEEE International Symposium on Field-Programmable Custom Computing Machines, April 1997, Print ISBN 0-8186-8159-4

Certified English Translation of PCT Application Publication No. WO00/62339 to Satoh

Michael J. Alexander, James P. Cohoon, Jared L. Colflesh, John Karro, and Gabriel Robins, Three-Dimensional Field-Programmable Gate Arrays, Proceedings of Eighth International Application Specific Integrated Circuits Conference, Sept. 1995

Complaint in Arbor Global Strategies v. Xilinx, 19-cv-01986 (D. Delaware) D.I. 1.

Michael B. Kleiner, et al., Modeling the Impact of 3-D-Technology on the Performance of the Memory Hierarchy of RISC Systems, IEEE 1995, Print ISBN 0-7803-2570-2

U.S. Patent No. 6,178,494 to Casselman

U.S. Patent No. 6,157,213 to Voogel

U.S. Patent No. 6,944,809 to Lai

U.S. Patent No. 6,369,608 to Lesea

Edward Tau, et al., A First Generation DPGA Implementation, Proceedings of FPD¿¿¿95 ¿¿¿ Third Canadian Workshop of Field-Programmable Devices, May 29-June 1, 1995, Montreal, Canada

Product Specification for XC4000E and XC4000X Series Field Programmable Gate Arrays, May 14, 1999

U.S. Patent Application Publication No. 2001/0026013 to Mess

U.S. Patent No. 5,914,906 to Iadanza et al.

U.S. Patent No. 5,878,051 to Sharma et al.

U.S. Patent No. 6,051,887 to Hubbard

Michael B. Kleiner, et al., Performance Improvement of the Memory Hierarchy of RISC-Systems by Application of 3-D Technology, Proceedings of the 1996 IEEE Transactions on Components, Packaging, and Manufacturing Technology, November 1996

U.S. Patent No. 5,781,031 to Bertin

U.S. Patent No. 6,222,276 to Bertin

U.S. Patent No. 5,581,498 to Ludwig

Michael J. Alexander, et al., Physical Layout for Three-Dimensional FPGAs, Fifth ACM/SIGDA Physical Design Workshop, pp. 142-149, April 1996

T. Kunio, et al., Three Dimensional ICs, Having Four Stacked Active Device Layers, Proceedings of International Technical Digest on Electron Devices Meeting, December 3-6, 1989, Print ISBN: 0-7803-0817-4

D. Bollman, et al., Three Dimensional Metallization for Vertically Integrated Circuits, Proceedings of MAM97 Materials for Advanced Metallization, March 16-19, 1997, Print ISSN: 1266-0167

David Maliniak, Memory-Chip Stacks Send Density Skyward, Electronic Design, August 22, 1994, 1994 Vol. 42, No. 17.

U.S. Patent No. 5,970,254 to Cooke

U.S. Patent No. 5,801,547 to Kean

Ayman Kayssi et al., FPGA-Based Internet Protocol Firewall Chip, ICECS 2000. Proceedings of ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), December 17-20, 2000, Print ISBN: 0-7803-6542-9

U.S. Patent No. 5,844,917 to Salem et al.

U.S. Patent No. 5,426,378 to Ong

John Villasenor et al., Configurable Computing Solutions for Automatic Target Recognition, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines (April 17-19, 1996), Print ISBN 0-8186-7548-9

U.S. Patent No. 6,313,522 to Akram

U.S. Patent No. 5,862,387 to Songer

U.S. Patent No. 6,237,029 to Master

Pierre Marchal, Field-Programmable Gate Arrays, ACM, Communications of the ACM, Vol. 42, No. 4 April 1999

Andre DeHon, The Density Advantage of Configurable Computing, IEEE, Computer, Vol. 33, Issue 4, April 2000, pp. 41-49, Print ISSN 0018-9162

Scheduling Order in Arbor Global Strategies v. Xilinx, 19-cv-01986 (D. Delaware) D.I. 47

U.S. Patent No. 7,126,214 to Huppenthal

U.S. Patent No. 4,855,905 to Estrada

U.S. Patent No. 6,451,626 to Lin

U.S. Patent Pub. 20040015905A1 to Huima

U.S. Patent No. 7,194,535 to Hannel

Japan¿¿¿s Push into Creative Semiconductor Research: 3-Dimensional ICs, Solid State Technology, March 1987

U.S. Patent No. 6,781,226 to Huppenthal

U.S. Patent No. 7,282,951 to Huppenthal

U.S. Patent No. RE42,035 to Huppenthal

File Wrapper of 6,781,226

File Wrapper of 7,126,214

File Wrapper of 7,282,951

File Wrapper of RE42,035

Penguin Dictionary of Electronics, 3d Ed. 1998 (entries: chip, die, memory, port)

Petitioner's Power of Attorney

John L. Hennessy & David A. Patterson, Computer Architecture, A Quantitative Approach, Morgan Kaufmann, 1990, pp. 466-469 (cache coherency problem)

Xilinx Formal Notice of Stipulation

U.S. Patent No. 5,656,548 to Zavracky

Declaration of Dr. Paul Franzon, Ph.D.

Petition for Inter Partes Review