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a ON Semiconductor et al. vs Invensas Corporation et al.

The detailed information for PTAB case with proceeding number IPR2020-01729 filed by Semiconductor Components Industries, LLC d/b/a ON Semiconductor et al. against Invensas Corporation et al. on Sep 30, 2020. This includes filing dates, application numbers, tech centers, patent numbers, and current case status.

Case Details

Proceeding Number: IPR2020-01729
Filing Date: Sep 30, 2020
Petitioner: Semiconductor Components Industries, LLC d/b/a ON Semiconductor et al.
Respondent: Invensas Corporation et al.
Status: Final Written Decision
Respondent Application Number: 09143723
Respondent Tech Center: 2800
Respondent Patent Number: 6232231
Institution Decision Date: Dec 17, 2020
Termination Date: Sep 1, 2021

Proceeding Documents

The table below shows documents filed in the case, listing each document name, filing date, document type, and filing party. Tracking these filings indicates the activity of the parties involved in the case, and the types of documents filed can provide insights into the legal strategies being employed.

Show Exhibit Documents

Document Name	Filing Date	Category	Filing Party
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Final Written Decision: original	Sep 1, 2021	PAPER	BOARD
PANEL CHANGE ORDER Conduct of the Proceedings 37 C.F.R. ¿¿ 42.5	Dec 28, 2020	PAPER	BOARD
Decision - Granting Institution of Inter Partes Review; Granting Motion for Joinder	Dec 17, 2020	PAPER	BOARD
Patent Owner Non-Opposition to Joinder Motion	Dec 4, 2020	PAPER	PATENT OWNER
Patent Owner Mandatory Notices	Oct 21, 2020	PAPER	PATENT OWNER
Patent Owner Power of Attorney	Oct 21, 2020	PAPER	PATENT OWNER
Notice of Accord Filing Date	Oct 8, 2020	PAPER	BOARD
U.S. Patent No. 6,232,231	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 6,093,631	Sep 30, 2020	EXHIBIT	PETITIONER
Integration of CMP Into Deep Sub-micron Multilevel Metallization Circuits by D. Pramanik et al., Proceedings of the First International Symposium on Chemical Mechanical Planarization in Integrated Circuit Device Manufacturing (Pramanik1997)	Sep 30, 2020	EXHIBIT	PETITIONER
CMP Applications for Sub-0.25m Process Technologies by D. Pramanik et al., Proceedings of the Second International Symposium on Chemical Mechanical Planarization in Integrated Circuit Device Manufacturing (Pramanik1998)	Sep 30, 2020	EXHIBIT	PETITIONER
Introduction to VLSI Systems by C. Mead and L. Conway (Mead) PART 1	Sep 30, 2020	EXHIBIT	PETITIONER
Digital Integrated Circuits by J. Rabaey (Rabaey) PART 1	Sep 30, 2020	EXHIBIT	PETITIONER
Digital Integrated Circuits by J. Rabaey (Rabaey) PART 3	Sep 30, 2020	EXHIBIT	PETITIONER
Digital Integrated Circuits by J. Rabaey (Rabaey) PART 4	Sep 30, 2020	EXHIBIT	PETITIONER
Chemical Mechanical Planarization of Microelectronic Materials by J. Steigerwald et al. (Steigerwald)	Sep 30, 2020	EXHIBIT	PETITIONER
Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing, by H. Landis et al., Thin Solid Films (1992) 1-7 (Landis)	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,948,573	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,639,679	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,928,959	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,721,172	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,943,590	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,602,423	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,652,465	Sep 30, 2020	EXHIBIT	PETITIONER
Declaration of Dr. Duane S. Boning	Sep 30, 2020	EXHIBIT	PETITIONER
Prosecution History for U.S. Patent No. 6,232,231	Sep 30, 2020	EXHIBIT	PETITIONER
The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes, by B. Stine et al., IEEE Trans. On Elec. Devices, Vol. 45 No. 3 March 1998, pp. 665-679 (Stine1998)	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,879,222	Sep 30, 2020	EXHIBIT	PETITIONER
Digital Integrated Circuits by J. Rabaey (Rabaey) PART 2	Sep 30, 2020	EXHIBIT	PETITIONER
Introduction to VLSI Systems by C. Mead and L. Conway (Mead) PART 2	Sep 30, 2020	EXHIBIT	PETITIONER
Introduction to VLSI Systems by C. Mead and L. Conway (Mead) PART 3	Sep 30, 2020	EXHIBIT	PETITIONER
Introduction to VLSI Systems by C. Mead and L. Conway (Mead) PART 4	Sep 30, 2020	EXHIBIT	PETITIONER
Principles of CMOS VLSI Design 2nd Edition by N. Weste and K. Eshraghian (Weste) PART 1	Sep 30, 2020	EXHIBIT	PETITIONER
Implementation of CMP-based design rules and pattern practices by L. E. Camilletti, Proc. IEEE/SEMI Adv. Semiconduct. Manufact. Conf., October 1995, pp. 2-4 (Camilletti)	Sep 30, 2020	EXHIBIT	PETITIONER
The role of dummy fill patterning practices on intra-die ILD thickness variation in CMP processes by B. Stine et al., Proc. VLSI Multilevel Interconnect Conf., June 1996, pp. 421-423 (Stine)	Sep 30, 2020	EXHIBIT	PETITIONER
Multilevel interconnect system for 0.35-m CMOS LSIs with metal dummy planarization process and thin tungsten wirings, by Ichikawa et al., VLSI Multilevel Interconnect Conf., June 1995, pp. 254-260 (Ichikawa)	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 5,923,563	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 6,103,626	Sep 30, 2020	EXHIBIT	PETITIONER
Claim Construction Order (Nov. 16, 2018) from Case 1:17-cv-01363-MN (D. Del.)	Sep 30, 2020	EXHIBIT	PETITIONER
Claim Construction Order (Oct. 26, 2018) from Case 2:17-CV-00670-RWS-RSP (E.D. Tx.)	Sep 30, 2020	EXHIBIT	PETITIONER
IPR2017-00831 Decision Denying Institution of Inter Partes Review (Paper 8)	Sep 30, 2020	EXHIBIT	PETITIONER
IPR2018-01401 Petition for Inter Partes Review of U.S. Patent No. 6,232,231	Sep 30, 2020	EXHIBIT	PETITIONER
IPR2018-01401 Decision to Terminate Proceeding (Paper 11)	Sep 30, 2020	EXHIBIT	PETITIONER
Feb. 24, 2003 Amendment from Prosecution of U.S. Patent No. 6,849,946	Sep 30, 2020	EXHIBIT	PETITIONER
Printout of Electrochemical Society webpage on 2/19/2020 of https://www.electrochem.org/dl/pv/published/1996/1996.htm	Sep 30, 2020	EXHIBIT	PETITIONER
U.S. Patent No. 6,109,775	Sep 30, 2020	EXHIBIT	PETITIONER
Email from Duane Boning dated March 10, 1998	Sep 30, 2020	EXHIBIT	PETITIONER
Principles of CMOS VLSI Design 2nd Edition by N. Weste and K. Eshraghian (Weste) PART 2	Sep 30, 2020	EXHIBIT	PETITIONER
"Principles of CMOS VLSI Design 2nd Edition" by N. Weste and K. Eshraghian ("Weste") PART 3	Sep 30, 2020	EXHIBIT	PETITIONER
PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 6,232,231	Sep 30, 2020	PAPER	PETITIONER
Power of Attorney	Sep 30, 2020	PAPER	PETITIONER
Motion for Joinder to Inter Parties Review IPR2020-00603	Sep 30, 2020	PAPER	PETITIONER