Micron Technology, Inc. et al. vs BeSang Inc.

Petitioner's Notice of Appeal

Judgment Final Written Decision

Other: Hearing transcript

Patent Owner's Updated Exhibit List

Patent Owner's Demonstratives

Petitioner's Updated List of Exhibits

Petitioner's Demonstratives

LEAP Practitioner Request and Verification Form (Petitioner)

Joint Stipulation To Modify Due Date To Exchange Demonstratives

ORDER Setting Oral Argument 37 C.F.R. § 42.70

Petitioner's Request for Oral Argument

Patent Owner's Request for Oral Argument

Patent Owner's Sur-Reply

Dr. Jack C. Lee Depo. Transcript (June 12, 2024)

Petitioner's Opposition to Patent Owner's Motion to Strike

Patent Owner's Motion to Strike

Patent Owner's Notice of Deposition of Dr. Jack C. Lee

Joint Stipulation to Modify Due Date 3

Patent Owner's Objections to Evidence

Petitioner's Reply to Patent Owner's Response

Y. Beilliard et al., Advances Toward Reliable High Density Cu–Cu Interconnects by Cu-SiO2 Direct Hybrid Bonding, 2014 International 3D Systems Integration Conference (3DIC) (2014)

Perrine Batude et al., 3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS, 2 IEEE J. Emerging and Selected Topics in Circuits and Systems 714-22 (2012)

Rafael Reif et al., Technology and Applications of Three- Dimensional Integration, 2004 Electrochemical Society Proceedings Volume 261-76 (2004)

Dr. Lee’s Deposition Errata Sheet

SEM Image

Two-level Stack of Watanabe’s Fig. 7

Four-level Stack of Watanabe’s Fig. 7

Certain Semiconductor Chips and Prods. Containing Same, ITC Inv. No. 337-TA-753, 2012 WL 927056 (Mar. 2, 2012)

Certain Semiconductor Chips and Prods. Containing Same, ITC Inv. No. 337-TA-753, 2012 WL 927056 (Mar. 2, 2012)

Declaration of Dr. Jack C. Lee in Support of Petitioner’s Reply to Patent Owner’s Response

Email thread from Sang-Yun Lee, dated Nov. 8-26, 2007

Sang-Yun Lee & Junil Park, Architecture of 3D Memory Cell Array on 3D IC, IEEE (2012)

Email thread from Scott DeBoer (Micron), dated Oct. 10, 2017

Email from Scott DeBoer (Micron), dated July 19, 2016

Sang-Yun Lee & Junil Park, History and Trend of 3-Dimensional Integrated Circuit

International Technology Roadmap for Semiconductors: Front End Processes (2003)

U.S. Patent No. 6,951,798

Gerald Lucovsky et al., Integration of Plasma-Assisted and Rapid Thermal Processing for Low-Thermal Budget Preparation of Ultra- Thin Dielectrics for Stacked-Gate Device Structures, 33 Jpn. J. Appl. Phys. Vol. 7061-70 (1994)

J. Wong et al., Rapid Thermal Annealing of Deposited 𝑆𝑖𝑂􀬶 Films, 35 Mat. Res. Soc. Symp. Proc. 514-20 (1985)

Dr. Steven A. Przybylski Deposition Transcript (Apr. 5, 2024)

D.E. Mercer et al., Will Thermal Budget Really Matter in the Future, 2001-9 Electrochemical Soc. Proceedings 247 (2000)

Jürgen Regner, An Analytical Approach to Quantify the Thermal Budget in Consideration of Consecutive Thermal Process Steps, 10th IEEE Int’l Conference on Advanced Thermal Processing of Semiconductors – RTP 15-20 (2002)

R. L. Smith & S. D. Collins, A Wafer-to-wafer Alignment Technique, 20 Sensors & Actuators 315-16 (1989)

Frank Niklaus et al., A Method to Maintain Wafer Alignment Precision During Adhesive Wafer Bonding, 107 Sensors & Actuators 273-78 (2003)

Updated Guidance for Making a Proper Determination of Obviousness, 89 Fed. Reg. 14,449-453 (Feb. 27, 2024), https://www.federalregister.gov/documents/2024/02/27/2024- 03967/updated-guidance-for-making-a-proper-determination-ofobviousness

Roberto Bez et al., Introduction to Flash Memory, 91 Proc. IEEE 489-502 (2003)

Paolo Pavan, Flash Memory Cells—An Overview, 85 Proc. IEEE 1248 (1997)

Keith Thompson, Electromagnetic Fast-Firing for the Rapid Thermal Processing of Silicon (Feb. 25, 2003) (Ph.D. dissertation, University of Wisconsin-Madison)

Keith Thompson et al., Direct Silicon-Silicon Bonding by Electromagnetic Induction Heating, 11 J. Microelectromechanical Sys. 285-92 (2002)

U.S. Patent No. 5,519,236

U.S. Patent No. 5,932,920

Petitioner’s Notice of Deposition of Dr. Steven A. Przybylski

Patent Owner's Response to Petition for Inter Partes Review

Bez, Intro to Flash Memory

Executive Summary, ITRS (2003)

'994 Patent, Fig. 12B (annotated by Dr. Lee)

'994 Patent, Fig. 12B (annotated by Dr. Lee)

'994 Patent, Fig. 12B (annotated by Dr. Lee)

'994 Patent, Fig. 12B (annotated by Dr. Lee)

Batude, 3-D Sequential Information (2012)

Dr. Jack C. Lee Depo. Transcript (Feb. 6, 2024)

Declaration of Steven A. Przybylski

CV of Steven A. Przybylski

Webster's Dictionary excerpt (2003)

Random House Dictionary excerpt (1997)

May, Fundamentals of Semiconductor Manufacturing (2006)(excerpts)

Keeth, DRAM Circuit Design Fundamental (2008) (excerpts)

Keeth, DRAM Circuit Design Tutorial (2001) (excerpts)

Itoh, VLSI Memory Chip Design (2001) (excerpts)

Interconnect, ITRS (2007)

2/16/2024 Board email

Joint Stipulation to Modify Due Date 1

Patent Owner's Amended Notice of Deposition of Dr. Jack C. Lee

Patent Owner's Notice of Deposition of Dr. Jack C. Lee

EXPUNGED

Petitioner's Updated Mandatory Notices Pursuant to 37 C.F.R. §42.8(a)(2)

Petitioner's Updated List of Exhibits

BeSang, Inc. v. Micron Technology Inc. et al., 2:23-CV-00028-JRG-RSP, D.I. 95 (E.D. Tex. Dec. 20, 2023), Order Granting Stipulation and Joint Motion to Stay Pending Inter Partes Review (“Order Granting Stay”)

Patent Owner's Objections to Evidence

Institution Decision: Grant

Order: Scheduling Order

Patent Owner's Preliminary Sur-Reply

9-14-2023 Email from Board Authorizing Preliminary Reply and Sur-Reply Briefing

Petitioner's Preliminary Reply In Support of Inter Partes Review of U.S. Patent No. 7,378,702

Letter dated September 21, 2023 to counsel for Patent Owner from John Kappos

Patent Owner's Preliminary Response

First Amended Docket Control Order, BeSang v. Micron (E.D. Tex. June 21, 2023)

Docket Re BeSang v. Micron (E.D. Tex.) (as of Aug. 28, 2023)

Defs' Patent L.R. 3-3 Invalidity Contentions, BeSang v. Micron (E.D. Tex. July 11, 2023)

Mutschler, Stanford, Korean nanofab center, EDN (Aug. 13, 2008)

Press Release, Micron and Intel Unveil New 3D NAND Flash Memory (Mar. 26, 2015)

Clarke, EE Times updates list of emerging startups (Feb. 2, 2009)

GSA Forum, Exploring the Potential of Emerging Semiconductor Technology (June 2011)

Frost & Sullivan, Looking Beyond TSV For 3D IC Technology (Mar. 2009)

Press Release, Micron and Intel Extend their Leadership (May 21, 2018)

Micron Unveils 3D NAND (Mar. 26, 2015) (video file)

Radar Scope, Semiconductor Times (Apr. 2007)

1-29-2007 Email from Peter Feeley to BeSang

7-30-2007 Email exchange between Tom Arnold, Sang-Yun Lee, and others

US District Courts – Federal Court Management Statistics (June 30, 2023)

Notice: Notice filing date accorded

Notice : Mandatory Notice

Notice : Power of Attorney

U.S. Patent No. 7,378,702 (“the ’702 Patent”)

Curriculum Vitae of Dr. Jack C. Lee

Prosecution History of U.S. Patent No. 7,378,702 (App. No. 10/934,270)

U.S. Patent No. 5,091,762 (“Watanabe”)

U.S. Patent Application Pub. No. US2002/0154556 (“Endoh”) [Part 1]

U.S. Patent Application Pub. No. US2002/0154556 (“Endoh”) [Part 2]

U.S. Patent Application Pub. No. US2002/0154556 (“Endoh”) [Part 3]

U.S. Patent Application Pub. No. US2002/0154556 (“Endoh”) [Part 4]

U.S. Patent Application Pub. No. US2002/0154556 (“Endoh”) [Part 5]

U.S. Patent Application Pub. No. US2002/0154556 (“Endoh”) [Part 6]

U.S. Patent No. 6,881,994 (“Lee”)

U.S. Patent No. 7,221,008 (“Matamis”)

G. Groeseneken et al., Basics of Nonvolatile Semiconductor Memory Devices

Philip M. Sailer et al., Creating 3D Circuits Using Transferred Films, IEEE

U.S. Patent No. 5,808,938 (“Tran”)

U.S. Patent No. 6,982,905 (“Nguyen”)

U.S. Patent No. 6,807,098 (“Jeong”)

Kee-Ho Yu et al., Real-Time Microvision System with Three-Dimensional

U.S. Patent No. 5,374,564 (“Bruel”)

Horacio Mendez, Silicon-on-Insulator: SOI Technology and Ecosystem

U.S. District Courts – Combined Civil and Criminal Federal Court Management

T. Mikolajick et al., The Future of Charge Trapping Memories

Complaint, BeSang Inc. v. Micron Tech., Inc., No. 2:23-cv-00028

Jim Handy, 3D NAND: Benefits of Charge Traps over Floating Gates

E. Bertagnolli et al., ROS: An Extremely High Density MASK ROM Technology

Tetsuo Endoh et al., Novel Ultrahigh-Density Flash memory

F. Nemati & J.D. Plummer, A Novel High Density, Low Voltage SRAM Cell

K.W. Lee et al., Three-Dimensional Shared Memory Fabricated Using Wafer

NAND vs. NOR Flash Memory, Toshiba America Electronic Components, Inc.

G.K. Celler & Sorin Crisoloveanu, Frontiers of Silicon-on-Insulator

Timeline, Soitec

G. Shahidi et al., Fabrication of CMOS on Ultrathin SOI

MicroChemicals, Further Processing of Silicon Wafers

Hiroshi Sakuraba et al., New Three-Dimensional High-Density

Declaration of Dr. Jack C. Lee

Petition for Inter Partes Review of U.S. Patent No. 7,378,702

Petitioner Micron Technology, Inc. et al.'s Power of Attorney