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IP Verse

Citadel Securities LLC - IPR2026-00151

Explore the PTAB proceeding IPR2026-00151 filed by Citadel Securities LLC on Dec 3, 2025. This includes filing dates, application numbers, tech centers, patent numbers, and current case status.

Case Details

Proceeding Number
IPR2026-00151
Filing Date
Dec 3, 2025
Petitioner
Citadel Securities LLC
Status
Pending
Respondent Application Number
17723145
Respondent Tech Center
2800
Respondent Patent Number
11575381

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Proceeding Documents

The table below shows documents filed in the case, listing each document name, filing date, document type, and filing party. Tracking these filings indicates the activity of the parties involved in the case, and the types of documents filed can provide insights into the legal strategies being employed.

Document NameFiling DateCategoryFiling Party

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Notice: Notice filing date accorded

Dec 5, 2025PAPERBOARD

U.S. Patent No. 11,575,381

Dec 3, 2025EXHIBITPETITIONER

Declaration of Kevin B. Stanton, Ph.D.

Dec 3, 2025EXHIBITPETITIONER

File History (U.S. Patent No. 11,575,381)

Dec 3, 2025EXHIBITPETITIONER

Altera White Paper - Synchronous Ethernet Solutions with Altera FPGAs

Dec 3, 2025EXHIBITPETITIONER

Stratix V Device Handbook

Dec 3, 2025EXHIBITPETITIONER

Silicon Labs Si4345-44 Family Reference Manual

Dec 3, 2025EXHIBITPETITIONER

Lockwood, A Low-Latency Library in FPGA Hardware (HFT)

Dec 3, 2025EXHIBITPETITIONER

HFT Solutions' Response in Opposition to Motion to Dismiss

Dec 3, 2025EXHIBITPETITIONER

Affidavit of Mina Chung (Altera)

Dec 3, 2025EXHIBITPETITIONER

Affidavit of Mina Chung (Stratix Handbook)

Dec 3, 2025EXHIBITPETITIONER

Affidavit of Mina Chung (Si5345 Manual)

Dec 3, 2025EXHIBITPETITIONER

HFT Solutions, LLC's Infringement Contentions

Dec 3, 2025EXHIBITPETITIONER

Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262

Dec 3, 2025EXHIBITPETITIONER

The Race to Zero Latency for High Frequency Trading

Dec 3, 2025EXHIBITPETITIONER

U.S. Patent No. 10,169,814

Dec 3, 2025EXHIBITPETITIONER

Irene Aldridge, High Frequency Trading (Second Edition)

Dec 3, 2025EXHIBITPETITIONER

Implementing Fractional PLL Reconfiguration with Altera PLL

Dec 3, 2025EXHIBITPETITIONER

Exploring Algorithmic Trading in Reconfigurable Hardware

Dec 3, 2025EXHIBITPETITIONER

Douglas J. Smith, HDL Chip Design

Dec 3, 2025EXHIBITPETITIONER

UltraScale Architecture Clocking Resources User Guide

Dec 3, 2025EXHIBITPETITIONER

Chip Hall of Fame: Xilinx XC2064 FPGA

Dec 3, 2025EXHIBITPETITIONER

List and Comparison of FPGA Companies

Dec 3, 2025EXHIBITPETITIONER

Understanding Clock Domain Crossing (CDC) Checks and Techniques

Dec 3, 2025EXHIBITPETITIONER

Floyd M. Gardner, Phaselock Techniques

Dec 3, 2025EXHIBITPETITIONER

Interactive Brokers Founder Changed Trading Forever (Barrons)

Dec 3, 2025EXHIBITPETITIONER

Wall Street's Quest to Process Data at the Speed of Light (Rubinow)

Dec 3, 2025EXHIBITPETITIONER

FPGA accelerated low-latency market data feed processing (Morris et al)

Dec 3, 2025EXHIBITPETITIONER

The Once and Future Ethernet

Dec 3, 2025EXHIBITPETITIONER

An Introduction to Synchronized Internet

Dec 3, 2025EXHIBITPETITIONER

A. Frank D'Souza, Design of Control Systems

Dec 3, 2025EXHIBITPETITIONER

Altera, Clock Networks and PLLs in Stratix V Devices

Dec 3, 2025EXHIBITPETITIONER

Notice: Power of Attorney

Dec 3, 2025PAPERPETITIONER

Petition for Inter Partes Review

Dec 3, 2025PAPERPETITIONER