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IP Verse

Citadel Securities LLC - IPR2026-00212

Explore the PTAB proceeding IPR2026-00212 filed by Citadel Securities LLC on Jan 9, 2026. This includes filing dates, application numbers, tech centers, patent numbers, and current case status.

Case Details

Proceeding Number
IPR2026-00212
Filing Date
Jan 9, 2026
Petitioner
Citadel Securities LLC
Status
Petition filed
Respondent Application Number
16937314
Respondent Tech Center
2800
Respondent Patent Number
10931286

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Proceeding Documents

The table below shows documents filed in the case, listing each document name, filing date, document type, and filing party. Tracking these filings indicates the activity of the parties involved in the case, and the types of documents filed can provide insights into the legal strategies being employed.

Document NameFiling DateCategoryFiling Party

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Notice: Power of Attorney

Jan 9, 2026PAPERPETITIONER

U.S. Patent No. 10,931,286

Jan 9, 2026EXHIBITPETITIONER

Declaration of Kevin B. Stanton, Ph.D

Jan 9, 2026EXHIBITPETITIONER

File History (U.S. Patent No. 10,931,286)

Jan 9, 2026EXHIBITPETITIONER

Altera White Paper - Synchronous Ethernet Solutions with Altera FPGAs

Jan 9, 2026EXHIBITPETITIONER

Stratix V Device Handbook

Jan 9, 2026EXHIBITPETITIONER

Silicon Labs Si4345-44 Family Reference Manual

Jan 9, 2026EXHIBITPETITIONER

Lockwood, A Low-Latency Library in FPGA Hardware (HFT)

Jan 9, 2026EXHIBITPETITIONER

(intentionally omitted)

Jan 9, 2026EXHIBITPETITIONER

Affidavit of Mina Chung (Altera)

Jan 9, 2026EXHIBITPETITIONER

Affidavit of Mina Chung (Stratix Handbook)

Jan 9, 2026EXHIBITPETITIONER

Affidavit of Mina Chung (Si5345 Manual)

Jan 9, 2026EXHIBITPETITIONER

HFT Solutions, LLC's Infringement Contentions

Jan 9, 2026EXHIBITPETITIONER

Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262

Jan 9, 2026EXHIBITPETITIONER

The Race to Zero Latency for High Frequency Trading

Jan 9, 2026EXHIBITPETITIONER

U.S. Patent No. 10,169,814

Jan 9, 2026EXHIBITPETITIONER

Irene Aldridge, High Frequency Trading (Second Edition)

Jan 9, 2026EXHIBITPETITIONER

Implementing Fractional PLL Reconfiguration with Altera PLL

Jan 9, 2026EXHIBITPETITIONER

Exploring Algorithmic Trading in Reconfigurable Hardware

Jan 9, 2026EXHIBITPETITIONER

Douglas J. Smith, HDL Chip Design

Jan 9, 2026EXHIBITPETITIONER

UltraScale Architecture Clocking Resources User Guide

Jan 9, 2026EXHIBITPETITIONER

Chip Hall of Fame: Xilinx XC2064 FPGA

Jan 9, 2026EXHIBITPETITIONER

List and Comparison of FPGA Companies

Jan 9, 2026EXHIBITPETITIONER

Understanding Clock Domain Crossing (CDC) Checks and Techniques

Jan 9, 2026EXHIBITPETITIONER

Floyd M. Gardner, Phaselock Techniques

Jan 9, 2026EXHIBITPETITIONER

Interactive Brokers Founder Changed Trading Forever (Barrons)

Jan 9, 2026EXHIBITPETITIONER

Wall Street's Quest to Process Data at the Speed of Light (Rubinow)

Jan 9, 2026EXHIBITPETITIONER

FPGA accelerated low-latency market data feed processing (Morris et al)

Jan 9, 2026EXHIBITPETITIONER

The Once and Future Ethernet

Jan 9, 2026EXHIBITPETITIONER

An Introduction to Synchronized Internet

Jan 9, 2026EXHIBITPETITIONER

A. Frank D'Souza, Design of Control Systems

Jan 9, 2026EXHIBITPETITIONER

Comparison of Challenged Claims

Jan 9, 2026EXHIBITPETITIONER

Petition for Inter Partes Review

Jan 9, 2026PAPERPETITIONER